Minimum Device Requirements - 3.0 English - PG194

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2024-12-18
Version
3.0 English

The following table lists the link widths and supported speed for a given speed grade.

Table 1. Minimum Device Requirements
Capability Link Speed Capability Link Widths Supported Speed Grades
AMD UltraScale+™ Device (PCIE4)
Gen1/Gen2 x1, x2, x4, x8, x16 -1, -1L, -1LV, -2, -2L, -2LV, -3 1
Gen3 x1, x2, x4 -1, -1L, -1LV, -2, -2L, -2LV, -3 1
x8, x16 -2, -2L, -3 1
AMD UltraScale+™ Devices (PCIE4C) 2
Gen1/Gen2 x1, x2, x4, x8, x16 -1, -2, -2L, -2LV, -3
Gen3 x1, x2, x4 -1, -2, -2L, -2LV, -3
x8 -1, -2, -2L, -2LV, -3
x16 -1, -2, -2L, -2LV, -3
Gen4 5 x1, x2, x4, x8 -2, -2L, -3
UltraScale Family
Gen1 x1, x2, x4, x8 -1, -2, -3, -1L, -1LV, -1H and -1HV 3
Gen2 x1, x2, x4, x8 -1, -2, -3, -1L, -1LV, -1H and -1HV 3
Gen3 x1, x2, x4 -1, -2, -3, -1L, -1LV, -1H and -1HV 3 , 4
Gen3 x8 -2, -3
7 Series Gen3 Family
Gen1 x1, x2, x4, x8 -3, -2, -1, -2L, -2G, -2I, -1M, -1I
Gen2 x1, x2, x4, x8 -3, -2, -1, -2L, -2G, -2I, -1M, -1I
Gen3 x1, x2, x4, x8 -3, -2, -2L, -2G, -2I
  1. -1L(0.95V), -1LV(0.90V), -2L(0.85V), -2LV(0.72V).
  2. AMD UltraScale+™ devices with high bandwidth memory (HBM) contain both PCIE4 and PCIE4C blocks. Only the PCIE4C blocks support Gen3 x16 in the -2LV speed grade.
  3. -1H and -1HV are available only for Virtex UltraScale devices. -1L and -1LV are available only for Kintex UltraScale devices.
  4. The Core Clock Frequency option must be set to 250 MHz for -1, -1LV, -1L, -1H and -1HV speed grades. The Core Clock Frequency option set to 500 MHz is supported for -3 and -2 speed grades only.
  5. For Gen4 mode restrictions, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).
Note: The minimum device requirements for the PCIE4CE are not yet available.
Note: Subject to the documented product features and minimum device requirements, this IP supports UltraScale+ devices with one or more PCIE4 / PCIE4C integrated blocks for PCIe. Based on available programmable logic resources, the following are not supported even if this IP is supported by the device architecture:
  • AMD Artix™ UltraScale+ FPGA devices AU15P and smaller in Gen4x8 link configuration with DMA (only AXI Bridge is supported in this link configuration).
  • Contact AMD Support for information about implementing this IP in devices containing at least one integrated block for PCIe but are not supported based on available programmable logic resources.