Interrupt Mask Register (Offset 0x13C) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2024-06-05
Version
3.0 English

The Interrupt Mask register controls whether each individual interrupt source can cause the interrupt line to be asserted. A one in any location allows the interrupt source to assert the interrupt line. The Interrupt Mask register initializes to all zeros. Therefore, by default no interrupt is generated for any event. The following table describes the Interrupt Mask register bits and values.

Table 1. Interrupt Mask Register
Bits Name Core Access Reset Value Description
0 Link Down RW 0 Enables interrupts for Link Down events when bit is set.
1 Reserved RO 0 Reserved
2 Reserved RO 0 Reserved
3 Hot Reset RW 0 Enables interrupts for Hot Reset events when bit is set. (Only writable for EP configurations, otherwise = 0)
4 Reserved RO 0 Reserved
7:5 Cfg Completion Status RW 0 Enables interrupts for config completion status. (Only writable for Root Port Configurations, otherwise = 0)
8 Cfg Timeout RO 0 Enables interrupts for Config (Cfg) Timeout events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
9 Correctable RO 0 Enables interrupts for Correctable Error events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
10 Non-Fatal RO 0 Enables interrupts for Non-Fatal Error events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
11 Fatal RO 0 Enables interrupts for Fatal Error events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
15:12 Reserved RO 0 Reserved
16 INTx Interrupt Received RO 0 Enables interrupts for INTx Interrupt events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
17 MSI Interrupt Received RO 0 Enables interrupts for MSI Interrupt events when bit is set. (Only writable for Root Port Configurations, otherwise = 0)
19:18 Reserved RO 0 Reserved
20 Slave Unsupported Request RW 0 Enables the Slave Unsupported Request interrupt when bit is set.
21 Slave Unexpected Completion RW 0 Enables the Slave Unexpected Completion interrupt when bit is set.
22 Reserved RW 0

Reserved.

This bit is previously mask Slave Completion Timeout in the Bridge IP. This functionality is now maintained by the PCIe IP.
23 Slave Error Poison RW 0 Enables the Slave Error Poison interrupt when bit is set.
24 Slave Completer Abort RW 0 Enables the Slave Completer Abort interrupt when bit is set.
25 Slave Illegal Burst RW 0 Enables the Slave Illegal Burst interrupt when bit is set.
26 Master DECERR RW 0 Enables the Master DECERR interrupt when bit is set.
27 Master SLVERR RW 0 Enables the Master SLVERR interrupt when bit is set.
28 Reserved RO 0 Reserved
31:29 Reserved RO 0 Reserved