Transmit CCIX Core Interface (256-Bit) - 3.0 English

Transmit CCIX Core Interface (256-Bit) - 3.0 English - PG194

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID

PG194

Release Date

2024-12-18

Version

3.0 English

The TX CCIX interface contains ports through which all user application CCIX data is transmitted. The following table defines the ports in the 256-bit transmit CCIX interface.

Table 1. 256-Bit Transmit CCIX Interface Port Descriptions
Port	Direction	Width	Description
s_axis_ccix_tx_tdata	Input	256	Receive data to the core from CCIX application.
s_axis_ccix_tx_tuser	Input	45	This set of signals contain sideband information on the TLP being transferred. These signals are valid when s_axis_ccix_tx_tvalid is High. The individual signals are defined in the following table.
s_axis_ccix_tx_tvalid	Input	1	The CCIX application asserts this signal whenever it presents valid data on s_axis_ccix_tx_tdata.
ccix_tx_credit_gnt	Output	1	This signal is asserted by the core to release credits. The core has a total of eight TX credits. After the VC1 link becomes active, the core first releases all the eight credits to the CCIX application, and then the core releases a credit as available. The CCIX application can transmit valid data when the application has credits available. Note: If the CCIX application drops valid between transmitting TLP packets, the application must grantee the continuation of TLP packets after ccix_tx_credit_gnt goes High at the core interface. Or The CCIX application can wait to accumulate the needed amount of credits before transmitting a TLP packet in order to avoid valid drop between packet.
ccix_tx_credit_rtn	Input	1	The CCIX application asserts this signal to return the credit to the core when the CCIX link is going to deactivate state.
ccix_tx_active_req	Input	1	This signal is asserted by CCIX application to move out of deactive (stop) state and into active state. This signal must remain High as long as the CCIX application requires the link to be in active state.
ccix_tx_active_ack	Output	1	The core asserts this signal in response to the ccix_tx_active_req from the CCIX application when the core is ready to accept packets being sent.
ccix_tx_deact_hint	Output	1	The core asserts this signal when the PCIe link want to go through a link reset, the CCIX application must use this signal to return the credits and move to link to deactive state.

Table 2. Sideband Signals in s_axis_ccix_tx_tuser (256-Bit Interface)
Bit Index	Name	Width	Description
1:0	is_sop[1:0]	2	Signals the start of a TLP in this beat. The encoding is as follows: 00: No new TLP starting in this beat. 01: A single new TLP starts in this beat. Its start position is indicated by is_sop0_ptr. 11: Two new TLPs are starting in this beat. The is_sop0_ptr signal provides the start position of the first TLP. The is_sop1_ptr signal provides the start position of the second TLP. 10: Reserved.
2	is_sop0_ptr	1	Indicates the position of the first byte of the first TLP starting in this beat: 0: Byte 0 1: Byte 16
3	is_sop1_ptr	1	Indicates the position of the first byte of the second TLP starting in this beat: 0: Reserved 1: Byte 16
5:4	is_eop[1:0]	2	Signals that a TLP is ending in this beat. These inputs are set in the final beat of a TLP. The encoding are as follows: 00: No TLPs ending in this beat. 01: A single TLP is ending in this beat. The is_eop0_ptr[2:0] signal provides the offset of the last Dword of this TLP. 11: Two TLPs are ending in this beat. is_eop0_ptr[2:0] provides the offset of the last Dword of the first TLP. is_eop1_ptr[2:0] provides the offset of the last Dword of the second TLP. 10: Reserved.
7:6	discontinue[1:0]	2	This signal can be asserted by the user application during a transfer if it has detected an error in the data being transferred and needs to abort the packet. The core nullifies the corresponding TLP on the link to avoid data corruption. The user logic can assert this signal in any beat of a TLP. It can either choose to terminate the packet prematurely in the cycle where the error was signaled, or continue until all bytes of the payload are delivered to the core. The discontinue signal can be asserted only when s_axis_ccix_tx_tvalid is High. Thus, once asserted, it should not be deasserted until the end of the packet.
10:8	is_eop0_ptr[2:0]	3	Indicates the offset of the last Dword of the first TLP ending in this beat. This input is valid when is_eop[0] is asserted.
13:11	is_eop1_ptr[2:0]	3	Indicates the offset of the last Dword of the second TLP ending in this beat. This input is valid when is_eop[1] is asserted.
45:14	data_parity[31:0]	32	Odd parity for the 256-bit data. When parity checking is enabled in the core, the user logic must set bit i of this bus to the odd parity computed for byte i of s_axis_ccix_tx_tdata. On detection of a parity error, the core nullifies the corresponding TLP on the link and reports it as an Uncorrectable Internal Error.