The IRQ Block registers are described in this section.
Address (hex) | Register Name |
---|---|
0x00 | IRQ Block Identifier (0x00) |
0x04 | IRQ Block User Interrupt Enable Mask (0x04) |
0x08 | IRQ Block User Interrupt Enable Mask (0x08) |
0x0C | IRQ Block User Interrupt Enable Mask (0x0C) |
0x10 | Reserved |
0x14 | Reserved |
0x18 | Reserved |
0x40 | IRQ Block User Interrupt Request (0x40) |
0x44 | Reserved |
0x48 | IRQ Block User Interrupt Pending (0x48) |
0x4C | Reserved |
0x80 | IRQ Block User Vector Number (0x80) |
0x84 | IRQ Block User Vector Number (0x84) |
0x88 | IRQ Block User Vector Number (0x88) |
0x8C | IRQ Block User Vector Number (0x8C) |
0xA0 | Reserved |
0xA4 | Reserved |
Bit Index | Default | Access Type | Description |
---|---|---|---|
31:20 | 12’h1fc | RO | DMA Subsystem for PCIe identifier |
19:16 | 4’h2 | RO | IRQ Identifier |
15:8 | 8’h0 | RO | Reserved |
7:0 | 8'h04 | RO |
Version 8'h01: 2015.3 and 2015.4 8'h02: 2016.1 8'h03: 2016.2 8'h04: 2016.3 8'h05: 2016.4 8'h06: 2017.1, 2017.2 and 2017.3 |
Bit Index | Default | Access Type | Description |
---|---|---|---|
[NUM_USR_INT-1:0] |
AXI Bridge Functional Mode: {NUM_USR_INT}'b1 DMA Functional Mode: 'h0 |
RW |
user_int_enmask User Interrupt Enable Mask 0: Prevents an interrupt from being generated when the user interrupt source is asserted. 1: Generates an interrupt on the rising edge of the user interrupt source. If the Enable Mask is set and the source is already set, a user interrupt will be generated also. |
Bit Index | Default | Access Type | Description |
---|---|---|---|
W1S |
user_int_enmask Bit descriptions are the same as in the following table. |
Bit Index | Default | Access Type | Description |
---|---|---|---|
W1C | user_int_enmask Bit descriptions are the same as in table: IRQ Block User Interrupt Enable Mask (0x04). |
Bit Index | Default | Access Type | Description |
---|---|---|---|
[NUM_USR_INT-1:0] | ‘h0 | RO |
user_int_req User Interrupt Request This register reflects the interrupt source AND’d with the enable mask register. |
Bit Index | Default | Access Type | Description |
---|---|---|---|
[NUM_USR_INT-1:0] | ‘h0 | RO |
user_int_pend User Interrupt Pending. This register indicates pending events. The pending events are cleared by removing the event cause condition at the source component. |
If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In Legacy interrupts only the two LSBs of each field should be used to map to INTA, B, C, or D.
Bit Index | Default | Access Type | Description |
---|---|---|---|
28:24 | 5’h3 | RW |
vector 3 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[3]. |
20:16 | 5’h2 | RW |
vector 2 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[2]. |
12:8 | 5’h1 | RW |
vector 1 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[1]. |
4:0 | 5’h0 | RW |
vector 0 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[0]. |
If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In Legacy interrupts only the 2 LSB of each field should be used to map to INTA, B, C, or D.
Bit Index | Default | Access Type | Description |
---|---|---|---|
28:24 | 5’h7 | RW | vector 7 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[7]. |
20:16 | 5’h6 | RW | vector 6 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[6]. |
12:8 | 5’h5 | RW | vector 5 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[5]. |
4:0 | 5’h4 | RW | vector 4 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[4]. |
If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In Legacy interrupts only the 2 LSB of each field should be used to map to INTA, B, C, or D.
Bit Index | Default | Access Type | Description |
---|---|---|---|
28:24 | 5’hB | RW |
vector 11 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[11]. |
20:16 | 5’hA | RW |
vector 10 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[10]. |
12:8 | 5’h9 | RW |
vector 9 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[9]. |
4:0 | 5’h8 | RW |
vector 8 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[8]. |
If MSI is enabled, this register specifies the MSI or MSI-X vector number of the MSI. In Legacy interrupts only the 2 LSB of each field should be used to map to INTA, B, C, or D.
Bit Index | Default | Access Type | Description |
---|---|---|---|
28:24 | 5’hF | RW |
vector 15 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[15]. |
20:16 | 5’hE | RW |
vector 14 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[14]. |
12:8 | 5’hD | RW |
vector 13 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[13]. |
4:0 | 5’hC | RW |
vector 12 The vector number that is used when an interrupt is generated by the user IRQ usr_irq_req[12]. |