The PHY Status/Control register (described in the following table) provides the status of the current PHY state, as well as control of speed and rate switching for Gen2-capable cores.
| Bits | Name | Core Access | Reset Value | Description |
|---|---|---|---|---|
| 0 | Link Rate is Gen2 | RO | 0 | Reports the current link rate. 0b = 2.5 GT/s (if bit[12] = 0), or 8.0GT/s (if bit[12] = 1) 1b = 5.0 GT/s |
| 2:1 | Link Width | RO | 0 | Reports the current link width. 00b = x1 01b = x2 10b = x4 11b = x8 |
| 8:3 | LTSSM State | RO | 0 | Reports the current Link Training and Status State Machine (LTSSM) state. Encoding is specific to the underlying integrated block. |
| 10:9 | Reserved | RO | 0 | Reserved |
| 11 | Link Up | RO | 0 | Reports the current PHY Link-up state. 1b: Link up 0b: Link down Link up indicates the core has achieved link up status, meaning the LTSSM is in the L0 state and the core can send/receive data packets. |
| 12 | Link Rate is Gen3 | RO | 0 | Reports the current link rate. 0b = see bit[0] 1b = 8.0 GT/s |
| 13 | Link Width is x16 | RO | 0 | Reports the current link width. 0b = See bit[2:1] 1b = x16 |
| 31:13 | Reserved | RO | 0 | Reserved |