Example 1 (32-bit PCIe Address Mapping) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2024-06-05
Version
3.0 English

This example shows the generic settings to set up three independent AXI BARs and address translation of AXI addresses to a remote 32-bit address space for PCIe. This setting of AXI BARs does not depend on the BARs for PCIe in the functional mode.

In this example, number of AXI BARs are 3, the following assignments for each range are made.

Aperture_Base_Address_0=0x00000000_12340000
Aperture_High_Address_0 =0x00000000_1234FFFF (64 Kbytes)
AXI_to_PCIe_Translation_0=0x00000000_56710000 (Bits 63-32 are zero in order
to produce a
32-bit PCIe TLP. Bits 15-0 must be zero based on the AXI BAR aperture size.
Non-zero
values in the lower 16 bits are invalid translation values.)
Aperture_Base_Address_1 =0x00000000_ABCDE000
Aperture_High_Address_1 =0x00000000_ABCDFFFF (8 Kbytes)
AXI_to_PCIe_Translation_1=0x00000000_FEDC0000 (Bits 63-32 are zero in order
to produce a
32-bit PCIe TLP. Bits 12-0 must be zero based on the AXI BAR aperture size.
Non-zero
values in the lower 13 bits are invalid translation values.)
Aperture_Base_Address_1 =0x00000000_FE000000
Aperture_High_Address_2 =0x00000000_FFFFFFFF (32 Mbytes)
AXI_to_PCIe_Translation_2=0x00000000_40000000 (Bits 63-32 are zero in order
to produce a
32-bit PCIe TLP. Bits 24-0 must be zero based on the AXI BAR aperture size.
Non-zero
values in the lower 25 bits are invalid translation values.)
Figure 1. Example 1 Settings
  • Accessing the Bridge AXI BAR_0 with address 0x0000_12340ABC on the AXI bus yields 0x56710ABC on the bus for PCIe.
Figure 2. AXI to PCIe Address Translation

  • Accessing the Bridge AXI BAR_1 with address 0x0000_ABCDF123 on the AXI bus yields 0xFEDC1123 on the bus for PCIe.
  • Accessing the Bridge AXI BAR_2 with address 0x0000_FFEDCBA on the AXI bus yields 0x41FEDCBA on the bus for PCIe.