The PCIe-XVC-VSEC and AXI-XVC have a slightly different register map that must be taken into account when designing XVC drivers and software. The register maps in the following tables show the byte-offset from the base address.
- The PCIe-XVC-VSEC base address must fall within the valid range of the PCIe Extended Configuration space. This is specified in the Debug Bridge IP configuration.
- The base address of an AXI-XVC Debug Bridge is the offset for the Debug Bridge IP peripheral that was specified in the Vivado Address Editor.
The following tables describe the register map for the Debug Bridge IP as an offset from the base address when configured for the From PCIe-Ext to BSCAN or From AXI to BSCAN modes.
| Register Offset | Register Name | Description | Register Type |
|---|---|---|---|
| 0x00 | PCIe Ext Capability Header | PCIe defined fields for VSEC use. | Read Only |
| 0x04 | PCIe VSEC Header | PCIe defined fields for VSEC use. | Read Only |
| 0x08 | XVC Version Register | IP version and capabilities information. | Read Only |
| 0x0C | XVC Shift Length Register | Shift length. | Read Write |
| 0x10 | XVC TMS Register | TMS data. | Read Write |
| 0x14 | XVC TDIO Register | TDO/TDI data. | Read Write |
| 0x18 | XVC Control Register | General control register. | Read Write |
| 0x1C | XVC Status Register | General status register. | Read Only |
| Register Offset | Register Name | Description | Register Type |
|---|---|---|---|
| 0x00 | XVC Shift Length Register | Shift length. | Read Write |
| 0x04 | XVC TMS Register | TMS data. | Read Write |
| 0x08 | XVC TDI Register | TDI data. | Read Write |
| 0x0C | XVC TDO Register | TDO data. | Read Only |
| 0x10 | XVC Control Register | General control register. | Read Write |
| 0x14 | XVC Status Register | General status register. | Read Only |
| 0x18 | XVC Version Register | IP version and capabilities information. | Read Only |