AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194) - 3.0 English - PG194

Document ID: PG194
Release Date: 2024-12-18
Version: 3.0 English

Introduction
Features
IP Facts
Overview
Feature Summary
Unsupported Features
Limitations
PCIe Transaction Type
PCIe Capability
Others
Licensing and Ordering
Product Specification
Standards
Performance and Resource Utilization
Minimum Device Requirements
Port Descriptions
Global Signals
AXI Slave Interface
AXI Master Interface
AXI4-Lite Control Interface
AXI Bridge for PCIe Gen3 MSI Signals
AXI Bridge for PCIe Gen3 MSI-X Signals
DMA/Bridge Subsystem for PCIe in Bridge Mode Interrupt Signals
PCIe Interface
Bridge Parameters
Memory Map
Bridge Register Memory Map
PCIe Configuration Space Header
Bridge Info Register (Offset 0x130)
Bridge Status and Control Register (Offset 0x134)
Interrupt Decode Register (Offset 0x138)
Interrupt Mask Register (Offset 0x13C)
Bus Location Register (Offset 0x140)
PHY Status/Control Register (Offset 0x144)
Root Port Status/Control Register (Offset 0x148)
Root Port MSI Base Register 1 (Offset 0x14C)
Root Port MSI Base Register 2 (Offset 0x150)
Root Port Error FIFO Read Register (Offset 0x154)
Root Port Interrupt FIFO Read Register 1 (Offset 0x158)
Root Port Interrupt FIFO Read Register 2 (Offset 0x15C)
Root Port Interrupt Decode 2 Register (Offset 0x160)
Root Port Interrupt Decode 2 Mask Register (Offset 0x164)
Root Port MSI Interrupt Decode 1 Register (Offset 0x170)
Root Port MSI Interrupt Decode 2 Register (Offset 0x174)
Root Port MSI Interrupt Decode 1 Mask Register (Offset 0x178)
Root Port MSI Interrupt Decode 2 Mask Register (Offset 0x17C)
Configuration Control Register (Offset 0x168)
VSEC Capability Register 2 (Offset 0x200)
VSEC Header Register 2 (Offset 0x204)
AXI Base Address Translation Configuration Registers (Offset 0x208 - 0x234)
DMA/Bridge Subsystem for PCIe Register Memory Map
IRQ Block Registers (0x2)
MSI-X Vector Table and PBA (0x8)
Enhanced Configuration Access Memory Map
Designing with the Core
General Design Guidelines
Shared Logic
Clocking
Reference Clock for PCIe Frequency Value
Resets
AXI Transactions for PCIe
Transaction Ordering for PCIe
BAR and Address Translation
BAR Addressing
Address Translation
Example 1 (32-bit PCIe Address Mapping)
Example 2 (64-bit PCIe Address Mapping)
Example 3
Example 4
Addressing Checks
Malformed TLP
Abnormal Conditions
Slave Bridge Abnormal Conditions
Illegal Burst Type
Completion TLP Errors
Unexpected Completion
Unsupported Request
Completion Timeout
Poison Bit Received on Completion Packet
Completer Abort
Master Bridge Abnormal Conditions
AXI DECERR Response
AXI SLVERR Response
Max Payload Size for PCIe, Max Read Request Size or 4K Page Violated
Completion Packets
Poison Bit
Zero Length Requests
Link Down Behavior
Endpoint
Interrupts
AXI Bridge for PCIe Gen3
Legacy Interrupts
MSI Interrupts
External MSI-X Interrupts
DMA/Bridge Subsystem for PCIe in Bridge Mode
Legacy Interrupts
MSI and Internal MSI-X Interrupts
Root Port
Power Limit Message TLP
Root Port Configuration Read
Root Port BAR
Configuration Transaction Timeout
Abnormal Configuration Transaction Termination Responses
Receiving Interrupts
Legacy Interrupt FIFO Mode
Legacy INTx Interrupt
MSI Interrupt
MSI-X Interrupt
Interrupt Decode Mode
Legacy INTx Interrupt
MSI Interrupt
MSI-X Interrupt
Tandem Configuration
Design Flow Steps
Customizing and Generating the Subsystem
Customizing the Core
AXI Bridge for PCIe Gen3
Basic Mode Tab
PCIe ID Tab
PCIe BARs Tab
PCIe Miscellaneous Tab
AXI BARs Tab
AXI Miscellaneous Tab
GT Settings Tab
Debug Options Tab
DMA/AXI Bridge Subsystem for PCI Express in AXI Bridge Mode
Basic Tab
PCIe ID Tab
PCIe BARs Tab
PCIe Miscellaneous Tab
AXI BARs Tab
AXI Misc Tab
Debug Options Tab
GT Settings Tab
Output Generation
Constraining the Subsystem
Required Constraints
System Integration
PCIe Clock Integration
Placement Constraints
Location Constraints
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Simulation
Post-Synthesis/Post-Implementation Netlist Simulation
Post-Synthesis Netlist Functional Simulation
Post-Implementation Netlist Functional Simulation
Synthesis and Implementation
Example Design
Endpoint Configuration of the AXI PCIe Block
AXI Verification IP Attached to the AXI Slave Interface
Customizing and Generating the Example Design
Simulation Design Overview
Implementation Design Overview
Example Design Elements
Example Design Output Structure
Test Bench
Root Port Model Test Bench for Endpoint
Architecture
Simulating the Example Design
Endpoint Model Test Bench for Root Port
Architecture
Simulating the Example Design
Example Use Mode
Upgrading
Migrating from AXI PCIe Gen2 to AXI Bridge for PCIe Gen3
Parameter Changes
Migrating from AXI Bridge for PCIe Gen3 to DMA/Bridge Subsystem for PCIe in AXI Bridge Mode
Parameter Changes
Port Changes
Memory Map Changes
Upgrading in the Vivado Design Suite
Parameter Changes
Port Changes
Debugging
Finding Help with AMD Adaptive Computing Solutions
Documentation
Answer Records
Master Answer Record for the Subsystem
Technical Support
Debug Tools
Vivado Design Suite Debug Feature
Reference Boards
Third-Party Tools
Hardware Debug
Transceiver Debug
Additional Debug Information
Interface Debug
AXI4-Lite Interfaces
Using the Xilinx Virtual Cable to Debug
Overview
Host PC XVC-Server Application
Host PC XVC-over-PCIe Driver
XVC-over-PCIe Enabled FPGA Design
XVC-over-PCIe Through PCIe Extended Configuration Space (PCIe-XVC-VSEC)
XVC-over-PCIe Through AXI (AXI-XVC)
XVC-over-PCIe Register Map
PCIe Ext Capability Header
PCIe VSEC Header (PCIe-XVC-VSEC only)
XVC Version Register (PCIe-XVC-VSEC only)
XVC Shift Length Register
XVC TMS Register
XVC TDO/TDI Data Register(s)
XVC Control Register
XVC Status Register
XVC Driver and Software
Special Considerations for Tandem or Dynamic Function eXchange Designs
Using the PCIe-XVC-VSEC Example Design
Generating a PCIe-XVC-VSEC Example Design
System Bring-Up
Compiling and Loading the Driver
Compiling and Launching the XVC-Server Application
Connecting the Vivado Design Suite to the XVC-Server Application
Run Time Considerations
CCIX Interface
Supported Configurations
Port Descriptions
CCIX Core Interfaces
Transmit CCIX Core Interface (256-Bit)
Receive CCIX Core Interface (256-Bit)
Transmit CCIX Core Interface (512-Bit)
Receive CCIX Core Interface (512-Bit)
Example Figures
CCIX-VC1 Credits
CCIX Activation/Deactivation
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

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