AXI Transactions for PCIe - 3.0 English

The following tables are the translation tables for AXI4-Stream and memory-mapped transactions.

For PCIe® requests with lengths greater than 1 Dword, the size of the data burst on the Master AXI interface will always equal the width of the AXI data bus even when the request received from the PCIe link is shorter than the AXI bus width.

Slave axi write strobe (wstrb) signal can be used to facilitate data alignment to an address boundary. Write strobe signal can be 0 in the beginning of a valid data cycle and it appropriately calculates an offset to the given address. However, the valid data identified by the write strobe signal must be continuous from the first byte enable to the last byte enable.

All transactions initiated at the Slave Bridge interface will be modified and metered by the IP as necessary. The Slave Bridge interface will conform to AXI4 specification and allow burst size up to 4KB, and the IP will split the transaction automatically according to PCIe Max Read Request Size (MRRS), Max Payload Size (MPS), and Read Completion Boundary (RCB), As a result of this operation, one request at the AXI domain result in multiple request at the PCIe domain, and the IP will adjust the number of issued PCIe request accordingly to avoid oversubscribing the available Completion buffer.

The Slave Bridge does not support narrow transfers natively on its AXI Slave interface. It is highly recommended for the AXI Master interfacing to the Slave Bridge to never generate a narrow transfers. However, the Bridge core can be customized to enable AXI Slave narrow burst support to allow interfacing to an AXI master which generates narrow transfers. These narrow transfers are typically generated as a result of interfacing with a smaller width AXI Master through an AXI Interconnect IP. When this option is enabled in the Bridge core, it adds AXI Upsizer IP as a sub-core, it is attached to the Slave Bridge AXI Slave interface. The internal AXI Upsizer IP is configured to modify the AXI transaction regardless of the modifiable bit in the AxCache signal to guarantee full transfers at the AXI Slave interface and it can produce a new AXI request that is longer than the original AXI request before it is processed into PCIe packets. The AXI Master which originated the read request or the destination PCIe device which is the recipient of the write request, never receives extra data, however, care must be taken when reading a destination device with destructive reads behavior (such as FIFOs or registers that are clear on read) because extra bytes read by core can alter the contents of those devices. Consequently, the extra null data beat that is generated as a result of the modified AXI request can impact the performance of the Bridge core. For more information on AXI Upsizer IP, see AXI Interconnect LogiCORE IP Product Guide (PG059).