System Integration - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2024-06-05
Version
3.0 English

A typical embedded system including the Bridge core is shown in . Some additional components to this system in the AMD Vivado™ IP integrator can include the need to connect the MicroBlaze™ ™ processor or AMD Zynq™ device Arm® processor peripheral to communicate with PCI Express® (in addition to the AXI4-Lite register port on the PCIe bridge). The AXI Interconnect provides this capability and performs the necessarily conversions for the various AXI ports that might be connected to the AXI Interconnect IP (see LogiCORE IP AXI to AXI Connector Data Sheet (DS803)).

The Bridge core can be configured with each port connection for an AXI Vivado IP integrator system topology. When instantiating the core, ensure the following bus interface tags are defined.

BUS_INTERFACE M_AXI
BUS_INTERFACE S_AXI
BUS_INTERFACE S_AXI_CTL