For all signals in this interface,
m_axi_* is used for the AXI Bridge for
PCIe Gen3 core, and m_axib_* is used for the DMA/Bridge Subsystem for
PCIe in AXI Bridge mode.
| Signal Name | I/O | Description |
|---|---|---|
|
m_axi(b)_awaddr[axi_addr_width-1:0] |
O | Master write address |
|
m_axi(b)_awlen[7:0] |
O | Master write burst length |
|
m_axi(b)_awsize[2:0] |
O | Master write burst size All write requests show the requested size is equal to the Master AXI data width except for 1DW request. 1DW request is supported as a special case. As an example, if the IP is configured for 128-bit Master AXI data width,m_axi(b)_awsize[2:0] will show '2' for 1DW request and '4' for 2DW request instead of '3'. Write data must be further masked with m_axi(b)_wstrb signal which will indicates valid byte lanes to avoid writing to disabled byte lanes. The IP doesn't support narrow burst on Master Interface. The above case of 'narrow transfer' is only for single beat transaction. |
|
m_axi(b)_awburst[1:0] |
O | Master write burst type |
|
m_axi(b)_awprot[2:0] |
O | Master write protection type |
|
m_axi(b)_awvalid |
O | Master write address valid |
|
m_axi(b)_awready |
I | Master write address ready |
|
m_axi(b)_wdata[axi_data_width-1:0] |
O | Master write data |
|
m_axi(b)_wstrb[axi_data_width/8-1:0] |
O | Master write strobe |
|
m_axi(b)_wlast |
O | Master write last |
|
m_axi(b)_wvalid |
O | Master write valid |
|
m_axi(b)_wready |
I | Master write ready |
| m_axi(b)_wuser | O | Reserved. Internally tied to GND. Note: This signal is disabled for AXI Bridge for PCI Express Gen3. This signal is also disabled for
the DMA/Bridge Subsystem for PCIe in AXI Bridge mode unless
CONFIG.parity_settings = Propagate_Parity is set.
|
|
m_axi(b)_bresp[1:0] |
I | Master write response |
|
m_axi(b)_bvalid |
I | Master write response valid |
|
m_axi(b)_bready |
O | Master response ready |
|
m_axi(b)_araddr[axi_addr_width-1:0] |
O | Master read address |
|
m_axi(b)_arlen[7:0] |
O | Master read burst length |
|
m_axi(b)_arsize[2:0] |
O | Master read burst size All read requests show the requested size is equal to the Master AXI data width except for 1DW request. 1DW request is supported as a special case. As an example, if the IP is configured for 128-bit Master AXI data width, this signal will show '2' for 1DW request and '4' for 2DW request instead of '3'. This behavior can be ignored if the request is not doing destructive reads; precaution must be taken for destructive register reads. The IP does not support narrow burst on Master Interface. The above case of narrow transfer is only for single beat transaction. |
|
m_axi(b)_arburst[1:0] |
O | Master read burst type |
|
m_axi(b)_arprot[2:0] |
O | Master read protection type |
|
m_axi(b)_arvalid |
O | Master read address valid |
|
m_axi(b)_arready |
I | Master read address ready. This signal only responds when Bus Master Enable bit is set in the Command register within the PCI® Configuration Space. |
|
m_axi(b)_rdata[axi_data_width-1:0] |
I | Master read data |
|
m_axi(b)_rresp[1:0] |
I | Master read response |
|
m_axi(b)_rlast |
I | Master read last |
|
m_axi(b)_rvalid |
I | Master read valid |
|
m_axi(b)_rready |
O | Master read ready |
| m_axi(b)_ruser | I | Reserved. Tie to GND. Note: This signal is disabled for AXI Bridge for PCI Express Gen3. This signal is also disabled for
the DMA/Bridge Subsystem for PCIe in AXI Bridge mode unless
CONFIG.parity_settings = Propagate_Parity is set.
|