Example Design Output Structure - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
Release Date
3.0 English

The following figure shows the output structure of the example design.

Figure 1. Example Design Output Structure

The following table provides a description of the contents of the example design directories.

Directory Description
project_1/axi_pcie3_example Contains all example design files.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/sources_1/imports/example_design/ Contains the top module for the example design, xilinx_axi_pcie3_ep.v.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/sources_1/ip/axi_pcie3 Contains the XDC file based on device selected, all design files and subcores used in axi_pcie, and the top modules for simulation and synthesis.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/sources_1/ip/axi_bram_ctrl_0 Contains block RAM controller files used in example design.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/sim_1/imports/simulation/dsport Contains all RP files, cgator and PIO files.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/sim_1/imports/simulation/functional Contains the test bench file.
project_1/axi_pcie3_example/axi_pcie3_example.srcs/constrs_1/imports/example_design Contains the example design XDC file.