Basic Mode Tab - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The initial customization screen shown in the following figure is used to define the basic parameters for the core, including the component name, PCIe® configuration, AXI parameters, and reference clock. The following figures show the parameters available for the Advanced Mode.

In the Basic Mode tab, the additional parameters available in Advanced Mode are applicable to AMD UltraScale™ ™ architecture devices only.

Figure 1. Basics Parameter Settings: Basic Mode Selected

Figure 2. Basic Parameter Settings: Advanced Mode Selected

Figure 3. Additional Basic Parameter Settings: Advanced Mode Selected

Component Name
Base name of the output files generated for the core. The name must begin with a letter and can be composed of these characters: a to z, 0 to 9, and “_.”
Note: The name cannot be the same as a core module name; for example, "axi_pcie" is a reserved name.
Mode
Allows you to select the Basic or Advanced mode of the configuration of core.
Device / Port Type
Indicates the PCI Express logical device type.
PCIe Block Location
Selects from the available integrated blocks to enable generation of location-specific constraint files and pinouts. This selection is used in the default example design scripts.
Enable GT Quad Selection
This parameter is used to enable the device/package migration. Applicable to AMD UltraScale™ devices only.
Number of Lanes
The core requires the selection of the initial lane width. Wider lane width cores can train down to smaller lane widths and consume more FPGA resource.
Maximum Link Speed
Indicates the maximum link speed supported by the design. Higher link speed cores are capable of training to lower link speeds and run at a higher clock frequency.
AXI Address Width
Indicates the AXI address width for the S_AXI and M_AXI interfaces, but does not affect the address width of the S_AXI_CTL interface.
AXI Data Width
Indicates the AXI data width for the S_AXI and M_AXI interfaces, but does not affect the data width of the S_AXI_CTL interface.
AXI Clock Frequency
Indicates the clock frequency that will be generated on the axi_aclk output. All AXI interfaces and a majority of the core outputs are synchronous to this clock.
Enable AXI Slave Interface
Allows the slave bridge to be enabled or disabled as desired by the system design. If only the master bridge is used the slave bridge can be disabled to conserve FPGA resources.
Enable AXI Master Interface
Allows the master bridge to be enabled or disabled as desired by the system design. If only the slave bridge is used, the master bridge can be disabled to conserve FPGA resources.
Reference Clock Frequency
Selects the frequency of the reference clock provided on the refclk reference clock input. This reference clock input corresponds to refclk for AMD Virtex™ 7 devices and sys_clk_gt for AMD UltraScale™ devices.
Enable Pipe Simulation
When selected, this option generates the core that can be simulated with PIPE interfaces connected.
Enable GT Channel DRP Ports
When checked, enables the GT channel DRP interface.
Enable PCIe DRP Ports
When checked, enables the PCIe DRP interface.
Tandem Mode
For supported devices only, this option allow you to choose the Tandem Configuration mode: None, Tandem PROM and Tandem PCIe.
Enable External STARTUP primitive
When checked, generates the STARTUP primitive external to the IP.
Use the dedicated PERST routing resources
Enables sys_rst dedicated routing for applicable UltraScale PCIe locations. This option is not applicable for Virtex 7 XT and UltraScale+ devices.
System Reset polarity
This parameter is used to set the polarity of the sys_rst ACTIVE_HIGH or ACTIVE_LOW.
CORE CLOCK Frequency
Available only when an UltraScale device is selected.

This parameter allows you to select the core clock frequencies.

For Gen3 link speed:
  • The values of 250 MHz and 500 MHz are available for selection for speed grade -2 or -3 and link width other than x8. For this configuration, this parameter is available when Advanced mode is selected.
  • For speed grades -2 or -3 and link width of x8, this parameter defaults to 500 MHz and is not available for selection.
  • For -1 speed grade (-1, -1L, -1LV,-1H and -1HV) and link width other than x8, this parameter defaults to 250 MHz and is not available for selection.

For Gen1 and Gen2 link speeds:

  • This parameter defaults to 250 MHz and is not available for selection.
    Note: When -1 or -1L, -1LV, -1H and -1HV speed grade is selected and non production parts of XCKU060 (ES2), XCKU115 (ES2) and VU440 (ES2) are selected, this parameter defaults to 250 MHz and is not available for selection.