DMA/Bridge Subsystem for PCIe Register Memory Map - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

This section lists Interrupt registers that are unique to DMA/Bridge Subsystem for PCIe in AXI Bridge mode only. These registers listed in this section are accessible through the AXI4-Lite Control interface when address bit[28] is set to 1'b1. When address bit[28] is set to 1'b0, all of these register fields are re-purposed for Bridge operation, which contains the same Bridge Memory map layout as listed in the previous section.

Table 1. DMA/Bridge Subsystem for PCIe Address Format
31:29 28 27:16 15:12 11:8 7:0
Reserved Register Table Select Reserved Target Reserved Byte Offset
Table 2. PCIe to DMA/Bridge Address Field Descriptions
Bit Index Field Description
31:29 Reserved Reserved
28 Register Table Select

1'b0: Select Bridge and ECAM registers listed in Bridge Memory Map in the previous section.

1'b1: Select Interrupt registers listed in this section.
27:16 Reserved

When bit[28] = 1'b0: Refer to Bridge Memory map.

When bit[28] = 1'b1: Reserved
15:12 Target

The destination submodule within the DMA

4’h0: Reserved

4’h1: Reserved

4’h2: IRQ Block

4’h3: Reserved

4’h4: Reserved

4’h5: Reserved

4’h6: Reserved

4'h8: MSI-X
11:8 Reserved This field must be 0.
7:0 Byte Offset The byte address of the register to be accessed within the target. Bits[1:0] must be 0.