Root Port MSI Interrupt Decode 2 Mask Register (Offset 0x17C)

Root Port MSI Interrupt Decode 2 Mask Register (Offset 0x17C) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

Document ID

PG194

Release Date

2024-06-05

Version

3.0 English

The Root Port MSI Interrupt Decode 2 Mask register controls whether MSI interrupt vector 32-63 are forwarded to the interrupt_out_msi_vec32to63 signal in Interrupt Decode mode. The Root Port MSI Interrupt Decode 2 Mask Register initializes to all zeros. The following table describes the register bits.

Table 1. Root Port MSI Interrupt Decode 2 Mask Register
Bits	Name	Core Access	Reset Value	Description
31:0	MSI Vector Status	RW	0	1 - This MSI vector is indicated in interrupt_out_msi_vec32to63 signal. 0 - This MSI vector is not indicated in interrupt_out_msi_vec32to63 signal. Bit index [x] indicates MSI vector x+32.