The AXI Base Address Translation Configuration registers and their offsets are shown in the following tables, and the register bits are described in the subsequent table. This set of registers can be used in two configurations based on the address width of the PCIe BARs. When the PCIe BAR is set to a 32-bit address space, then the translation vector should be placed into the AXIBAR2PCIEBAR_nL register where n is the PCIe BAR number. When the BAR is set to a 64-bit address space, then the most significant 32 bits are written into the AXIBAR2PCIEBAR_nU and the least significant 32 bits are written into AXIBAR2PCIEBAR_nL. Care should be taken so that invalid values are not written to the address translation registers.
Offset | Bits | Register Mnemonic |
---|---|---|
0x208 | 31-0 | AXIBAR2PCIEBAR_0U |
0x20C | 31-0 | AXIBAR2PCIEBAR_0L |
0x210 | 31-0 | AXIBAR2PCIEBAR_1U |
0x214 | 31-0 | AXIBAR2PCIEBAR_1L |
0x218 | 31-0 | AXIBAR2PCIEBAR_2U |
0x21C | 31-0 | AXIBAR2PCIEBAR_2L |
0x220 | 31-0 | AXIBAR2PCIEBAR_3U |
0x224 | 31-0 | AXIBAR2PCIEBAR_3L |
0x228 | 31-0 | AXIBAR2PCIEBAR_4U |
0x22C | 31-0 | AXIBAR2PCIEBAR_4L |
0x230 | 31-0 | AXIBAR2PCIEBAR_5U |
0x234 | 31-0 | AXIBAR2PCIEBAR_5L |
Bits | Name | Core Access | Reset Value | Description |
---|---|---|---|---|
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_0(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_0 = 64 bits), then reset value = C_AXIBAR2PCIEBAR_0(63 to 32) if (C_AXIBAR2PCIEBAR_0 = 32 bits), then reset value = 0x00000000 |
To create the address for PCIe–this is the value substituted for the most significant 32 bits of the AXI address. |
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_1(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_1 = 64 bits), then reset value = C_AXIBAR2PCIEBAR_1(63 to 32) if (C_AXIBAR2PCIEBAR_1 = 32 bits), then reset value = 0x00000000 |
To create the address for PCIe– this is the value substituted for the most significant 32 bits of the AXI address. |
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_2(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_2 = 64 bits), then reset value = C_AXIBAR2PCIEBAR_2(63 to 32) if (C_AXIBAR2PCIEBAR_2 = 32 bits), then reset value = 0x00000000 |
To create the address for PCIe–this is the value substituted for the most significant 32 bits of the AXI address. |
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_3(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_3 = 64 bits) then reset value = C_AXIBAR2PCIEBAR_3(63 to 32) if (C_AXIBAR2PCIEBAR_3 = 32 bits) then reset value = 0x00000000 |
To create the address for PCIe–this is the value substituted for the most significant 32 bits of the AXI address. |
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_4(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_4 = 64 bits), then reset value = C_AXIBAR2PCIEBAR_4(63 to 32) if (C_AXIBAR2PCIEBAR_4 = 32 bits), then reset value = 0x00000000 |
To create the address for PCIe–this is the value substituted for the most significant 32 bits of the AXI address. |
31-0 | Lower Address | R/W | C_AXIBAR2PCIEBAR_5(31 to 0) | To create the address for PCIe–this is the value substituted for the least significant 32 bits of the AXI address. |
31-0 | Upper Address | R/W |
if (C_AXIBAR2PCIEBAR_5 = 64 bits), then reset value = C_AXIBAR2PCIEBAR_5(63 to 32) if (C_AXIBAR2PCIEBAR_5 = 32 bits), then reset value = 0x00000000 |
To create the address for PCIe–this is the value substituted for the most significant 32 bits of the AXI address. |