BAR Addressing - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)

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3.0 English

Aperture_Base_Address_n represents Aperture Base Address of nth BAR in GUI

Aperture_High_Address_n represents Aperture High Address of nth BAR in GUI

AXI to PCIe Translation_n represents AXI to PCIe_translation of nth BAR in GUI

Aperture_Base_Address n and Aperture_High_Address_n are used to calculate the size of the AXI BAR n and during address translation to PCIe address.

  • Aperture_Base_Address_n provides the low address where AXI BAR n starts and will be regarded as address offset 0x0 when the address is translated.
  • Aperture_High_Address_n is the high address of the last valid byte address of AXI BAR n. (For more details on how the address gets translated, see Address Translation.)

The difference between Aperture_Base_Address_n and Aperture_High_Address_n is your AXI BAR n size. These values must be set accordingly such that the AXI BAR n size is a power of two and must have at least 4K.

When a packet is sent to the Bridge core (outgoing PCIe packets), the packet must have an address that is in the range of Aperture_Base_Address_n and Aperture_High_Address_n. For a design that has an AXI Master with a potential of generating an address outside of this range, you must attach an additional AXI Interconnect core or provide an external address filtering logic. Any packet that is received by the AXI Interconnect core that has an address outside of this range is responded to with a SLVERR and prevented from progressing into the Bridge core. When the IP integrator is used, these parameters are derived from the Address Editor tab within the IP integrator. The Address Editor sets the AXI Interconnect as well as the core so the address range matches, and the packet is routed to the core only when the packet has an address within the valid range. AXI Address width is limited to 48 bits.