Bus Location Register (Offset 0x140) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2023-11-24
Version
3.0 English

The Bus Location register reports the Bus, Device, and Function number, and the Port number for the PCIe port (see the following table).

Table 1. Bus Location Register
Bits Name Core Access Reset Value Description
2:0 Function Number RO 0 Function number of the port for PCIe. Hard-wired to 0.
7:3 Device Number RO 0 Device number of port for PCIe. For Endpoint, this register is RO and is set by the Root Port.
15:8 Bus Number RO 0 Bus number of port for PCIe. For Endpoint, this register is RO and is set by the external Root Port.
23:16 Port Number RW 0

Sets the Port number field of the Link Capabilities register.

EP: Always Read 0 and is not writeable.

RP: Is writeable.
31:24 Reserved RO 0 Reserved