Root Port MSI Interrupt Decode 2 Register (Offset 0x174) - 3.0 English

AXI Bridge for PCI Express Gen3 Subsystem Product Guide (PG194)
Document ID
PG194
Release Date
2024-06-05
Version
3.0 English

The Root Port MSI Interrupt Decode 2 register reads from this location return MSI vector 32-63 source status. Data from each read follows the format shown in the following table. For non-Root Port cores, reads return 0.

Table 1. Root Port MSI Interrupt Decode 2 Register
Bits Name Core Access Reset Value Description
31:0 MSI Vector Number RW1C 0 MSI vector number. Bit index [x] indicates MSI vector x+32.