UART Transmit FIFO Register (UART_TX_FIFO) - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

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3.2 English

This 16-entry-deep FIFO contains data to be output by the UART using JTAG. The FIFO bit definitions are shown in Table 17. Data to be transmitted is written into this register. When a write request is issued while the FIFO is full, a bus error (SLVERR) is generated and the data is not written into the FIFO. This is a write-only location. Issuing a read request to the transmit data FIFO generates the read acknowledgment with zero data. The following table shows the location for data on the AXI interface. The register is only implemented if C_USE_UART is set to 1.

Table 1. UART Receive FIFO Register (UART_TX_FIFO)
Reserved UART_TX
31 8 7 0
Table 2. UART Transmit FIFO Register Bit Definitions
Bits Name Access Reset Value Description
31:8 - R 0 Reserved
7:0 UART_TX R 0 UART Transmit Data