AXI4-Stream Trace Packets - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

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3.2 English

The trace packets for AXI4-Stream are intended to be further processed, in particular by the Zynq TPIU (see the Zynq-7000 SoC Technical Reference Manual (UG585)). The M_AXIS_TID signals are used to indicate which MicroBlaze processor has generated a specific packet. Each packet transmits 32 18-bit trace items, and consists of 18 32-bit words. The default packet encoding, when C_TRACE_PROTOCOL is 0, is illustrated in the following table. The AXI4-Stream also supports the alternate trace protocol, when C_TRACE_PROTOCOL is 1.

Table 1. AXI4-Stream Default Trace Packet Encoding
Trace Item Packet Word (w) and Bits Trace Item Packet Word (w) and Bits
0 w2[1:0], w0[15:0] 16 w11[1:0], w9[15:0]
1 w2[3:2], w0[31:16] 17 w11[3:2], w9[31:16]
2 w2[5:4], w1[15:0] 18 w11[5:4], w10[15:0]
3 w2[7:6], w1[31:16] 19 w11[7:6], w10[31:16]
4 w4[9:8], w2[23:8] 20 w13[9:8], w11[23:8]
5 w4[11:10], w3[7:0], w2[31:24] 21 w13[11:10], w12[7:0], w11[31:24]
6 w4[13:12], w3[23:8] 22 w13[13:12], w12[23:8]
7 w4[15:14], w4[7:0], w3[31:24] 23 w13[15:14], w13[7:0], w12[31:24]
8 w6[17:16], w4[31:16] 24 w15[17:16], w13[31:16]
9 w6[19:18], w5[15:0] 25 w15[19:18], w14[15:0]
10 w6[21:20], w5[31:16] 26 w15[21:20], w14[31:16]
11 w6[23:22], w6[15:0] 27 w15[23:22], w15[15:0]
12 w8[25:24], w7[7:0], w6[31:24] 28 w17[25:24], w16[7:0], w15[31:24]
13 w8[27:26], w7[23:8] 29 w17[27:26], w16[23:8]
14 w8[29:28], w8[7:0], w7[31:24] 30 w17[29:28], w17[7:0], w16[31:24]
15 w8[31:30], w8[23:8] 31 w17[31:30], w17[23:8]
Figure 1. AXI4-Stream Default Trace Packet Structure