IP Facts - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

Document ID
Release Date
3.2 English
LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Versal™ ACAP, UltraScale+™ , UltraScale™ , Zynq®-7000 SoC, 7 series
Supported User Interfaces AXI4, AXI4-Lite
Resources Performance and Resource Use web page
Provided with Core
Design Files RTL
Example Design Not Provided
Test Bench Not Provided
Constraints File Not Provided
Simulation Model VHDL Behavioral
Supported S/W Driver 2 Standalone and Linux
Tested Design Flows 3
Design Entry Vivado® Design Suite
Simulation For supported simulators, see the Xilinx Design Tools: Release Notes Guide.
Synthesis Vivado Synthesis
Release Notes and Known Issues Master Answer Record: 54413
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Xilinx Support web page
  1. For a complete list of supported devices, see the Vivado® IP catalog.
  2. Standalone driver details can be found in the Vitis™ software platform directory (<install_directory>/Vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
  3. For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide.