Customizing and Generating the Core - 3.2 English

This section includes information about using Xilinx® tools to customize and generate the core in the Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.

The MDM core parameters are divided into three categories: Debug, UART and Advanced. When using the Vivado IP integrator, the address for the JTAG-based UART is auto-generated.

The Customize IP dialog box is shown in the following figure.

Figure 1. Customize IP Dialog Box

Number of MicroBlaze debug ports

Sets the number of ports available to connect to MicroBlaze processors.

Enable Debug Register Access From AXI

Enables the functionality to access JTAG Debug registers from AXI and the AXI4-Lite slave interface.

Enable AXI Memory Access From Debug

Enables the functionality to access memory directly from JTAG, using the AXI4 master interface and the LMB master interfaces.

Enable Cross Trigger

Enables the cross trigger functionality, and the external cross-trigger interfaces. Cross trigger is not available when selecting AXI parallel debug.

Enable JTAG UART

Enables the JTAG UART and the AXI4-Lite slave interface to access the UART registers.

Select External Trace Output Interface

Enables trace output functionality, and selects the output interface: External, AXI4-Stream or AXI4-Master. External trace is not available when selecting AXI parallel debug.

External Trace Data Width

Defines the data width for the trace output interface External and AXI4-Stream: 2, 4, 8, 16, or 32 bits.

Specify the JTAG user-defined register used

Select JTAG user-defined register. Can be set to USER1, USER2, USER3, or USER4. Should never need to be changed from USER2, unless there is a conflict with another IP core in the system.

Select BSCAN location

Selects whether internal or external BSCAN is used, or disables BSCAN. Should normally be set to INTERNAL in an embedded system. Should be set to EXTERNAL or EXTERNAL HIDDEN when debugging with the Xilinx Virtual Cable (XVC) using the Debug Bridge. Can be set to NONE to disable BSCAN completely, when only Debug register access is used and no software debug is required.

Number of External Trigger Inputs

Defines the number of external trigger input interfaces to use when cross trigger is enabled.

Number of External Trigger Outputs

Defines the number of external trigger output interfaces to use when cross trigger is enabled.