Parameter Values - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

To tailor an MDM core uniquely for a specific system, certain features can be parameterized in the core design. This allows you to configure a design that only uses the resources required by the system. The features that can be parameterized in MDM designs are shown in the following table.

Table 1. MDM Design Parameters
Feature / Description Parameter Name Allowable Values

Default

Value

VHDL

Type
System Parameters
Target family C_FAMILY See IP Facts Virtex®-7 string
AXI Master address width C_M_AXI_ADDR_WIDTH 32-64 32 integer
LMB address size C_ADDR_SIZE 32-64 32 integer
Debug Parameters
Number of MicroBlaze™ debug ports C_MB_DBG_PORTS 0–32 1 1 integer
Enable Debug register access from AXI C_DBG_REG_ACCESS 0,1 0 integer
Enable AXI memory access from debug C_DBG_MEM_ACCESS 0,1 0 integer
Enable cross trigger 3 C_USE_CROSS_TRIGGER 0,1 0 integer
UART Parameters
Enable JTAG UART C_USE_UART 0,1 1 integer
Trace Parameters 3
Enable Trace Output C_TRACE_OUTPUT 0,1,2,3 0 integer
External and AXI4-Stream Trace Data Width C_TRACE_DATA_WIDTH 2,4,8,16,32 0 integer
External Trace Clock Input Frequency 2 C_TRACE_CLK_FREQ_HZ

Output clock frequency

multiplied by 2

 200 integer
External Trace Clock Phase 2 C_TRACE_CLK_OUT_PHASE 0–360 90 integer
External Trace Protocol 2 C_TRACE_PROTOCOL

0 = DEFAULT

1 = ALTERNATE

 1 integer
External Trace ID 2 C_TRACE_ID 1–110 110 integer
Advanced Parameters
Specifies the JTAG user-defined register used C_JTAG_CHAIN

1 = USER1

2 = USER2

3 = USER3

4 = USER4

 2 integer
Select BSCAN location C_USE_BSCAN

0 = INTERNAL

2 = EXTERNAL

3 = NONE

4 = EXTERNAL HIDDEN

 0 integer
Define BSCAN id 2 C_BSCANID 0 - 0xFFFFFFFF 0x4900300 integer
MicroBlaze Debug connection 2 C_DEBUG_INTERFACE

0 = SERIAL

1 = PARALLEL

2 = AXI

 0 integer
Number of external trigger inputs C_TRIG_IN_PORTS 0,1,2,3,4 1 integer
Number of external trigger outputs C_TRIG_OUT_PORTS 0,1,2,3,4 1 integer
External trigger reset value 2 C_EXT_TRIG_RESET_VALUE 0x00000–0xFFFFF 0xF1234 integer
Avoid SRL16 and SRL32 FPGA primitives 2 C_AVOID_PRIMITIVES 0,1 0 integer
  1. A value of 0 is legal and can be used if the MDM core is set up to only access AXI memory
  2. Not available in the Customize IP dialog box
  3. Not available when C_DEBUG_INTERFACE = 2 (AXI).

In addition to the parameters listed in this table, there are also parameters that are inferred for each AXI interface in the tools. Through the design, these inferred parameters control the behavior of the AXI Interconnect. For a complete list of the interconnect settings related to the AXI interface, see the AXI Interconnect LogiCORE IP Product Guide (PG059).