Parallel debug can be selected to improve timing in cases where timing closure is difficult to achieve with serial debug, in particular on stacked silicon interconnect (SSI) devices where the MDM core is placed in the master super logic region (SLR), and one or more MicroBlaze™ cores are placed in other regions. In this case it is suitable to configure both the MDM and MicroBlaze™ to use AXI parallel debug, which allows clocking of the debug signals between MDM and MicroBlaze™ using an AXI Register Slice. See AXI Interconnect LogiCORE IP Product Guide (PG059) for more information on how to use the AXI Register Slice.
When using internal BSCAN in SSI devices, the MDM placement is constrained to the master Super Logic Region (SLR1).