AXI4-Master Trace Buffer Low Address Debug Register - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

This register defines the AXI4-Master low address of the external trace memory buffer, with a 64KB granularity. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.

Table 1. AXI4-Master Trace Buffer Low Address Debug Register
Reserved Low Address
C_M_AXI_ADDR_WIDTH - 1 C_M_AXI_ADDR_WIDTH-17 0
Table 2. AXI4-Master Trace Buffer Low Address Debug Register Bit Definitions
Bits Name Access Reset Value Description
N:N-16 Reserved N/A 0

Reserved

N = C_M_AXI_ADDR_WIDTH - 1
N-17:0 Low Address W 0x0000

AXI4-Master low address of memory trace buffer. This is the 16-48 most significant bits of the address.

N = C_M_AXI_ADDR_WIDTH - 1