AXI4 Master Interface Signals - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English
Table 1. AXI4 Master I/F Signals (C_DBG_MEM_ACCESS = 1 or C_TRACE_OUTPUT = 3)
Signal Name Interface I/O Initial State Description
M_AXI_ACLK M_AXI I - AXI Clock
M_AXI_ARESETN I - AXI Reset, active-Low
M_AXI_AWID[C_M_AXI_THREAD_ID_WIDTH-1:0] O 0x0 Write Address ID
M_AXI_AWADDR[C_M_AXI_ADDR_WIDTH-1:0] O 0x0 Write Address
M_AXI_AWLEN[7:0] O 0x0 Write Address Length
M_AXI_AWSIZE[2:0] O 0x2 Write Address Size
M_AXI_AWBURST[1:0] O 0x1 Write Address Burst
M_AXI_AWLOCK O 0 Write Address Lock
M_AXI_AWCACHE[3:0] O 0x3 Write Address Cache
M_AXI_AWPROT[2:0] O 0x2 Write Address Protection
M_AXI_AWQOS[3:0] O 0x0 Write Address QoS
M_AXI_AWVALID O 0 Write Address Valid
M_AXI_AWREADY I - Write Address Ready
M_AXI_WDATA[C_M_AXI_DATA_WIDTH-1:0] O 0x0 Write Data
M_AXI_WSTRB[C_M_AXI_DATA_WIDTH/8-1:0] O 0x0 Write Strobes
M_AXI_WLAST O 0 Write Last
M_AXI_WVALID O 0 Write Valid
M_AXI_WREADY I - Write Ready
M_AXI_BRESP[1:0] I - Write Response
M_AXI_BID[C_M_AXI_THREAD_ID_WIDTH-1:0] I - Write Response ID
M_AXI_BVALID I - Write Response Valid
M_AXI_BREADY O 0 Write Response Ready
M_AXI_ARID[C_M_AXI_THREAD_ID_WIDTH-1:0] O 0x0 Read Address ID
M_AXI_ARADDR[C_M_AXI_ADDR_WIDTH-1:0] O 0x0 Read Address
M_AXI_ARLEN[7:0] O 0x0 Read Address Length
M_AXI_ARSIZE[2:0] O 0x0 Read Address Size
M_AXI_ARBURST[1:0] O 0x1 Read Address Burst
M_AXI_ARLOCK O 0 Read Address Lock
M_AXI_ARCACHE[3:0] O 0x3 Read Address Cache
M_AXI_ARPROT[2:0] O 0x2 Read Address Protection
M_AXI_ARQOS[3:0] O 0x0 Read Address QoS
M_AXI_ARVALID O 0 Read Address Valid
M_AXI_ARREADY I - Read Address Ready
M_AXI_RID[C_M_AXI_THREAD_ID_WIDTH-1:0] M_AXI I - Read ID
M_AXI_RDATA[C_M_AXI_DATA_WIDTH-1:0] I - Read Data
M_AXI_RRESP[1:0] I - Read Response
M_AXI_RLAST I - Read Last
M_AXI_RVALID I - Read Valid
M_AXI_RREADY O 0 Read Ready