This section contains information about constraining the core in the Vivado Design Suite.
Required Constraints
This section is not applicable for this IP core.
Device, Package, and Speed Grade Selections
This section is not applicable for this IP core.
Clock Frequencies
This section is not applicable for this IP core.
Clock Management
The MDM Debug logic is fully synchronous with the BSCAN module. Internally BUFG primitives are instantiated to buffer the DRCK clock from the BSCAN module.
The MDM JTAG-based UART and Debug register access is fully synchronous to the AXI4-Lite slave bus interface clock, and isolated from the BSCAN clock region with FIFOs and synchronization flip-flops when BSCAN is used.
The JTAG Memory Access AXI4 master interface and LMB master interfaces are fully synchronous to the AXI4 master clock, and isolated from the BSCAN clock region with FIFOs and synchronization flip-flops.
When MicroBlaze™ parallel debug interface is selected (C_DEBUG_INTERFACE > 0) all Debug register access is fully synchronous to the AXI4-Lite slave bus interface clock. The clocking of the connected processors depends on the used interface:
- In case C_DEBUG_INTERFACE is set to 1 (PARALLEL), the same clock must be used to clock the AXI4-Lite slave bus interface and all connected MicroBlaze processors.
- In case C_DEBUG_INTERFACE is set to 2 (AXI), different clocks can be used by the MDM and the connected MicroBlaze processors, since the AXI interconnect provides clock conversion.
Clock Placement
This section is not applicable for this IP core.
Banking
This section is not applicable for this IP core.
Transceiver Placement
This section is not applicable for this IP core.
I/O Standard and Placement
This section is not applicable for this IP core.