Feature Summary - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

Document ID
Release Date
3.2 English
  • Enables JTAG-based debugging of one or more MicroBlaze™ processors.
  • Instantiates one BSCAN primitive, or allows an external BSCAN to be used. In devices that contain more than one BSCAN primitive, the MDM core uses the USER2 BSCAN by default.
  • External BSCAN also supports connection to the Debug Bridge LogiCORE™ IP, to use the Xilinx® Virtual Cable (XVC) for debugging over non-JTAG interfaces.

    In Versal devices the external BSCAN is normally hidden and the Control, Interfaces and Processing System (CIPS) BSCAN is automatically connected by the Vivado® Design Suite, which provides a transparent functionality equivalent to other devices. However, it is possible to manually connect the CIPS BSCAN to the external BSCAN, if necessary. For more information on CIPS, see the Control, Interface and Processing System LogiCORE IP Product Guide (PG352).

  • Includes a UART with a configurable slave bus interface which can be configured for an AXI4-Lite interconnect. The UART TX and RX signals are transmitted over the device JTAG port to and from the Xilinx System Debugger (XSDB) tool. The UART behaves in a manner similar to the LogiCORE IP AXI (UART) Lite core.
  • Provides a configurable AXI4 master port for direct access to memory from JTAG. This allows fast program download, as well as transparent memory access when the connected MicroBlaze processors are executing. Extended address up to 64 bits is supported when MicroBlaze is configured to use 64-bit mode.
  • Allows software to control debug and observe debug status through the AXI4-Lite slave interface. This is particularly useful for software performance measurements and analysis, using the MicroBlaze extended debug functionality for performance monitoring.
  • Includes a cross-trigger capability, which enables routing of trigger events between connected MicroBlaze processors, as well as an external interface compatible with the Zynq®-7000 Processing System, Zynq® UltraScale+™ MPSoC, and Versal™ Control, Interfaces and Processing System.
  • Includes support for external trace interfaces to funnel and store MicroBlaze program trace in external storage. Program trace from connected MicroBlaze processors can be directly output on an external interface, stored in external memory via the AXI4 master port, or transmitted on an AXI4-Stream interface compatible with the Zynq-7000 Processing System.
  • Supports MicroBlaze parallel debug access, designed to provide faster direct access to MicroBlaze debug registers, and to improve timing compared to serial debug.

    In general, it is recommended to only use this feature when software debug through JTAG is not required, because otherwise the MDM must perform a serial to parallel conversion of the JTAG signals, which requires additional logic.