External Trace Control Debug Register - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

This register defines and starts continuous or timed test pattern generation, as well as defines direct or delayed trigger outputs on trace start and/or stop events. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.

A trigger is encoded by setting TRACE_CTL = 1 and TRACE_DATA[1:0] = 10.

Table 1. External Trace Control Debug Register
Reserved Test Pattern Select Trigger Enable TPT TPC Test Pattern Repeat Trigger Delay
31 14 13 10 9 8 7 0
Table 2. External Trace Control Debug Register Bit Definitions
Bits Name Access

Reset Value

 Description
31 - 14 Reserved N/A 0 Reserved
13 W1, STO W 0

Generate walking-ones test pattern, either for a duration defined by TPR when the TPT bit is set, or continuously when the TPC bit is set.

Output a trigger when trace is stopped in any processor.
12 W0, DSTO W 0

Generate walking-zeros test pattern, either for a duration defined by TPR when the TPT bit is set, or continuously when the TPC bit is set.

Output a trigger when trace is stopped after the delay defined by TD in any processor.
11 A5, STA W 0

Generate AA/55 test pattern, either for a duration defined by TPR when the TPT bit is set, or continuously when the TPC bit is set.

Output a trigger when trace is started in any processor.
10 F0, DSTA W 0

Generate FF/00 test pattern, either for a duration defined by TPR when the TPT bit is set, or continuously when the TPC bit is set.

Output a trigger when trace is started after the delay defined by TD in any processor.
9 TPT W 0 Generate timed test patterns for the duration defined by TPR, for the defined patterns W1, W0, A5, and F0 in sequence. One or more of the W1, W0, A5, and F0 bits must be set.
8 TPC W 0 Generate a continuous test pattern, either the pattern W1, W0, A5, or F0. Only one of the W1, W0, A5, and F0 bits must be set.
7 - 0 TPR, TD W 0x00

Defines a test pattern duration for timed test patterns in TRACE_CLK clock cycles, 0 - 255.

Defines trigger delay for DSTOP and DSTA triggers in 256 TRACE_CLK clock cycle intervals, 0, 256, 512, …, 65280.