The control register contains the enable interrupt bit and reset for the receive and transmit data FIFO. This is write only register. Issuing a read request to the control register generates the read acknowledgment with zero data. Bit assignment in the register is described in the following tables. The register is only implemented if C_USE_UART is set to 1.
Reserved | UART_CTRL | ||
31 | 5 | 4 | 0 |
Bits | Name | Access | Reset Value | Description |
---|---|---|---|---|
31-5 | Reserved | N/A | 0 | Reserved |
4 | Interrupt Enabled | W | 0 |
Enable interrupt for the MDM JTAG UART 0 = Disable interrupt signal 1 = Enable interrupt signal |
3 | Reserved | N/A | 0 | Reserved |
2 | Clear EXT_BRK signal | W | 0 |
Clear the EXT_BRK signal set by JTAG 0 = Do nothing 1 = Clear the signal |
1 | Reset RX FIFO | W | 1 |
Reset/clear the receive FIFO Writing a 1 to this bit position clears the receive FIFO 0 = Do nothing 1 = Clear the receive FIFO |
0 | Reset TX FIFO | W | 1 |
Reset/clear the transmit FIFO Writing a 1 to this bit position clears the transmit FIFO 0 = Do nothing 1 = Clear the transmit FIFO |