AXI4-Master Trace Current Address Debug Register - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

This register defines the first free location in the AXI4-Master external memory buffer. The register is incremented by 0x50 (20 32-bit words) for every trace packet written to the external memory buffer. This register is a read-only register. Issuing a write request has no effect.

If the FS bit is cleared in the AXI4-Master Trace Control Debug register, the current address will wrap around to the low address, defined by the AXI4-Master Trace Buffer Low Address, when it would have incremented past the high address, defined by the AXI4-Master Trace Buffer High Address.

The current address is reset to the low address, defined by the AXI4-Master Trace Buffer Low Address, by writing to the AXI4-Master Trace Control Debug register.

Table 1. AXI4-Master Trace Current Address Debug Register
Current Address
C_M_AXI_ADDR_WIDTH - 1 0
Table 2. AXI4-Stream Trace Control Debug Register Bit Definitions
Bits Name Access Reset Value Description
N:0 Current Address R 0x0 AXI4-Master current address of memory trace buffer. This is the full address of the first free location in the buffer.

N = C_M_AXI_ADDR_WIDTH-1