| TRACE_DATA[C_TRACE_DATA_WIDTH-1:0] |
TRACE |
O |
- |
Connection to external trace equivalent to the
Zynq Trace Packet Output, TPIU, port (see the
Zynq-7000 SoC Technical Reference Manual (UG585)) |
| TRACE_CTL |
O |
- |
| TRACE_CLK
1
|
I |
- |
| TRACE_CLK_OUT
2
|
O |
- |
- The nominal frequency of
TRACE_CLK is 200 MHz. If another clock frequency is used, the
parameter C_TRACE_CLK_FREQ_HZ is set from the connected input
clock (by propagation in Vivado IP Integrator) if possible, but
must otherwise be manually changed accordingly.
- The frequency of
TRACE_CLK_OUT is TRACE_CLK divided by 2, nominally 100 MHz with
a 90° phase shift, to create a sample point at a stable point of
the outputs. The phase shift can be adjusted manually with the
parameter C_TRACE_CLK_OUT_PHASE if necessary.
|