AXI4-Lite Slave Interface Signals - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English
Table 1. AXI4-Lite Slave Interface Signals (C_DBG_REG_ACCESS = 1)
Signal Name Interface I/O Initial State Description
S_AXI_ACLK S_AXI I - AXI Clock
S_AXI_ARESETN I - AXI Reset, active-Low
S_AXI_AWADDR[C_S_AXI_ADDR_WIDTH-1:0] I - Write Address
S_AXI_AWVALID I - Write Address Valid
S_AXI_AWREADY O 0 Write Address Ready
S_AXI_WDATA[C_S_AXI_DATA_WIDTH-1:0] I - Write Data
S_AXI_WSTB[C_S_AXI_DATA_WIDTH/8-1:0] I - Write Strobes
S_AXI_WVALID I - Write Valid
S_AXI_WREADY O 0 Write Ready
S_AXI_BRESP[1:0] O 0x0 Write Response
S_AXI_BVALID O 0 Write Response Valid
S_AXI_BREADY I - Write Response Ready
S_AXI_ARADDR[C_S_AXI_ADDR_WIDTH-1:0] I - Read Address
S_AXI_ARVALID I - Read Address Valid
S_AXI_ARREADY O 0 Read Address Ready
S_AXI_RDATA[C_S_AXI_DATA_WIDTH-1:0] I - Read Data
S_AXI_RRESP[1:0] O 0x0 Read Response
S_AXI_RVALID O 0 Read Valid
S_AXI_RREADY I - Read Ready