AXI4-Master Trace Status Debug Register - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

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3.2 English

This register defines whether trace has wrapped when the external memory buffer is full, and whether an AXI4-Master write has failed with a non-zero response. This register is a read-only register. Issuing a write request has no effect.

The status is cleared by writing to the AXI4-Master Trace Control Debug register.

Table 1. AXI4-Master Trace Status Debug Register
Reserved Wrap Response
31 3 2 1 0
Table 2. AXI4-Master Trace Status Debug Register Bit Definitions
Bits Name Access Reset Value Description
31 - 3 Reserved N/A 0 Reserved
2 Wrap R 0 This bit indicates if the current address has wrapped around.
1 - 0 Response R 00 The AXI4-Master write response, M_AXI_BRESP. The response is sticky - as soon as a non-zero response has occurred, the bits remain set.