AXI Slave Register Space - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)
Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

The following table describes the MDM core registers accessible through the AXI4-Lite slave interface.

Table 1. MDM Core AXI4-Lite Slave Registers
Register Name Size (bits) Address Offset Access Description
JTAG UART Registers (C_USE_UART = 1)
UART_RX_FIFO 8 0x00 R JTAG UART receive data
UART_TX_FIFO 8 0x04 W JTAG UART transmit data
UART_STATUS 8 0x08 R JTAG UART status
UART_CTRL 8 0x0C W JTAG UART control
Debug Register Access (C_DBG_REG_ACCESS = 1)
DBG_STATUS 1 0x10 R Debug register access status

bit 0 - Access lock acquired
DBG_CTRL 20 0x10 W Debug register access control
DBG_DATA 32 0x14 R/W Debug register access data
DBG_LOCK 16 0x18 W Debug register access lock
Parallel Debug Register Access (C_DBG_REG_ACCESS = 1, C_DEBUG_INTERFACE > 0)
PCCTRLR 8 0x5440 W MicroBlaze Performance Counter Control
PCCMDR 5 0x5480 W MicroBlaze Performance Counter Command
PCSR 2 0x54C0 R MicroBlaze Performance Counter Status
PCDRR 32 0x5580 R MicroBlazeRead data or Write Performance Counter Data Read
PCDWR 32 0x55C0 W MicroBlaze Performance Counter Data Write
TCTRLR 22 0x5840 W MicroBlaze Trace Control
TCMDR 4 0x5880 W MicroBlaze Trace Command
TSR 18 0x58C0 R MicroBlaze Trace Status
TDRR 18 0x5980 R MicroBlaze Trace Data Read
PCTRLR 8 0x5C40 W MicroBlaze Profiling Control
PLAR 30 0x5C80 W MicroBlaze Profiling Low Address
PHAR 30 0x5CC0 W MicroBlaze Profiling High Address
PBAR 9-14 0x5D00 W MicroBlaze Profiling Buffer Address
PDRR 36 0x5D80-0x5D84 R MicroBlaze Profiling Data Read
PDWR 32 0x5DC0 W MicroBlaze Profiling Data Write

The JTAG UART registers are identical to the AXI UART Lite registers (see the AXI UART Lite LogiCORE IP Product Guide (PG142)), except that the Status register bits 5–7 (OverrunError, Frame Error, Parity Error) are never set, and the Control register bit 2 is not reserved.

The Parallel Debug Access registers are MicroBlaze registers directly accessed through parallel debug interface (see the MicroBlaze Processor Reference Guide (UG984)). The MicroBlaze processors selected when accessing these registers are determined by the Which MicroBlaze Debug register.

The MDM core always responds to accesses within the defined address space. When Parallel Debug Register Access is enabled, the address space is 0x0000–0x7FFF; when Debug Register Access is enabled it is 0x00–0x1F; when JTAG UART is enabled it is 0x0–0xF. For any unused addresses, or when the Debug Register Access is locked, write requests are ignored and read requests return zero data.