Memory Access - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

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3.2 English

When using the JTAG memory access, the AXI4 Master should be connected to access the system memory accessible by the connected MicroBlazeâ„¢ cores, usually through the processor cache interfaces M_AXI_DC and M_AXI_IC. Depending on the AXI interconnect topology, this might exclude peripheral I/O accessed through the processor peripheral interface M_AXI_DP. The LMB Master ports should be connected to access the LMB local memory of the corresponding processor. This can be done by adding an additional LMB slave input to the data-side LMB block RAM Interface Controller (see the LMB BRAM Interface Controller LogiCORE IP Product Guide (PG112)).