UART Receive FIFO Register (UART_RX_FIFO) - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

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3.2 English
This 16-entry-deep FIFO contains data received by the UART from JTAG. The FIFO bit definitions are shown in the following table. Reading this register results in reading the data word from the top of the FIFO. When a read request is issued to an empty FIFO, a bus error (SLVERR) is generated and the result is undefined. The register is a read-only register. Issuing a write request to the receive data FIFO does nothing but generates a successful write acknowledgment. The following table shows the location for data on the AXI slave interface. The register is only implemented if C_USE_UART is set to 1.
Table 1. UART Receive FIFO Register (UART_RX_FIFO)
Reserved UART_RX
31 8 7 0
Table 2. UART Receive FIFO Register Bit Definitions
Bits Name Access Reset Value Description
31:8 - R 0 Reserved
7:0 UART_RX R 0 UART Receive Data