AXI4-Master Trace Control Debug Register - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

Document ID
PG115
Release Date
2021-01-21
Version
3.2 English

This register defines whether trace is stopped when the external memory buffer is full. This register is a write-only register. Issuing a read request has no effect, and undefined data is read.

The effect of setting the FS bit to one is that the current address will not wrap, and trace data will not be stored beyond the end of the memory buffer. This results in keeping the oldest trace data.

The effect of clearing the FS bit to zero is that the current address will wrap, the status register Wrap bit will be set, and the most recent trace data will be available, discarding older data, when the memory buffer becomes full.

Table 1. AXI4-Master Trace Control Debug Register
Reserved FS
31 1 0
Table 2. AXI4-Master Trace Control Debug Register Bit Definitions
Bits Name Access Reset Value Description
31 - 1 Reserved N/A 0 Reserved
0 Full Stop W 0 When this bit is set to 1, trace will stop when the external memory trace buffer is full, i.e. when the next packed would cause the current address to be incremented past the buffer high address.