VIO Core Considerations - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

When using AXIS-VIO cores, consider the following:

  • Signals connected to AXIS-VIO input probes must be synchronous to the clock connected to the AXIS-VIO clk port on the AXIS-VIO core. Connecting signals that are not synchronous to the clk port results in a clock domain crossing at the AXIS-VIO input probe port.
  • Signals driven from AXIS-VIO output probes are asserted and deasserted synchronous to the clock connected to the AXIS-VIO clk port on the AXIS-VIO core.
  • The AXIS-VIO core has a relatively low refresh rate because it is intended to replace low speed board I/O, such as push-buttons or light-emitting diodes (LEDs). To capture high-speed signals, consider using the ILA core.