Identifying Timing Violations Root Cause - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

For setup, you must first analyze the worst violation of each clock group. A clock group refers to all intra, inter, and asynchronous paths captured by a given clock.

For hold, all violations must be reviewed as follows:

  • Before routing, review only violations over 0.5 ns.
  • After routing, start with the worst violation.