Using IMUX Registers to Improve Timing to Hard Macros - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

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2024.1 English

IMUX registers are located in the IRI_QUAD sites that drive hard macros in the PL, which you can use to improve timing. All hard macros in the PL, such as RAMB36, RAMB18, URAM288, DSP58, and GTYP_QUAD, have IMUX register flip-flops that drive the input pins of these hard macros. You can apply IMUX Register (IMR) constraints to flip-flops in your design to automatically take advantage of this hardware feature during design placement.

In the following example, the data paths to the CH*_TXDATA[*] pins of a GTYP_QUAD are taking advantage of the IMR flip-flops. Using this method to constrain the input flip-flops that drive the hard macros can ease timing closure on these paths, because the routing from IMUX register to hard macro input is dedicated and therefore not impacted by suboptimal placement or congestion.
set_property IMR TRUE [get_cells -of [get_pins -leaf -of [get_nets -of [get_pins fmx_pcs_raw_inst/GT/CH*_TXDATA[*]]] -filter DIRECTION==OUT] -filter PRIMITIVE_GROUP==REGISTER]

The following figure shows the resulting placement and connectivity from setting the IMR property to TRUE.

Figure 1. IMR Property Set to TRUE