Debugging the System - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

When programming programmable device images (PDIs) on the Versal device, you must ensure the device is in a state ready for programming and device initialization. Because Versal device programming uses the PMC, it is critical that the PMC block is powered and the system clock is stable prior to programming. It is also critical that the power domains used by the image are fully powered prior to configuration. Finally, it is important that the device is not held in reset.

When connecting to the device, if the part name is not detected in the software tools, the software might show a name similar to XVJTAG40 for a vc1902 device. This commonly occurs if the device is being held in reset. Under these conditions, first check the reset line and power supplies. If these are all stable, the secondary cause might be due to a lockdown of the device. This can occur when the device is booted in a mode other than JTAG, which can lead the configuration engine to enter a lockdown state. To fix this issue, set the device mode pins to JTAG and then reboot.

After the device is in a stable state, programming the PDI might report errors. The errors from the PLM might report a slave boot error. When these messages occur, it is important to connect the UART to the system to get a more detailed report of the errors.