Improving Logic Levels - 2024.2 English - UG1388

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)
Document ID
UG1388
Release Date
2024-12-18
Version
2024.2 English

Throughout the design cycle, you must verify that the logic level distribution fits the clock frequency goals for the target AMD device family and device speed grade.

Global retiming is enabled by default to improve design performance but at the expense of power and compile time. To recover some power and compile time, consider disabling global retiming and instead limit retiming to specific hierarchical blocks with timing violations on paths with relatively high numbers of logic levels. When the paths in the fanin or fanout of the longest paths have fewer logic levels and are contained within a small or medium hierarchical module, you can use the BLOCK_SYNTH.RETIMING block-level synthesis strategy.
Note: You can set BLOCK_SYNTH.RETIMING to either 1 or 0. Set the value to 1 when retiming is turned off by default but retiming is desired on a specific area. Set the value to 0 when retiming is turned on by default but retiming is not desired on a specific area.

The following figure shows a critical paths with five LUTs, constrained by a 600 MHz clock. The REG2 destination flop drives a timing path with a single LUT that is included one hierarchy up from REG2.

Figure 1. Schematic Showing Critical Path with Five Logic Levels

In addition to using the Schematic window in the Vivado IDE, you can use the report_design_analysis -logic_level_distribution command to review the distribution of logic levels for specific paths. This allows you to determine how many paths need to be rebalanced to improve the timing QoR.

You can use the retiming_forward and retiming_backward attributes available in Vivado synthesis to control the optimization on a specific register or a path. Using these attributes applies retiming optimization on a specific set of paths rather than on the top module or submodules, which reduces the area overhead. You can apply these attributes in the RTL or in the XDC file. For more information, including usage and restrictions, see the Vivado Design Suite User Guide: Synthesis (UG901).

Note: Like the BLOCK_SYNTH.RETIMING property, you can set both retiming_forward and retiming_backward either to 0 or 1 depending on whether retiming is desired or not desired on a specific register.

The following figure shows 58 paths with five logic levels within the inst1/inst2 hierarchy constrained with the 600 MHz clock and 32 paths with only one logic level.

Figure 2. Logic Level Distribution with Default Synthesis Optimization

Vivado synthesis can rebalance the logic levels by moving the registers from the low logic level paths into the high logic level paths. In this example, you can add the following constraint to the synthesis XDC file to perform retiming on the inst1/inst2 hierarchy:

set_property BLOCK_SYNTH.RETIMING 1 [get_cells inst1/inst2]

After rerunning synthesis with the same global settings and the updated XDC file, you can run regular timing analysis on the inst1/inst2 timing paths or rerun the report_design_analysis command to verify that the longest paths have fewer logic levels, as shown in the following figure. The critical path is now REG0 > 3 LUTs > REG2 (backward retimed), and the path from REG2 to REG4 has three logic levels.

Figure 3. Logic Level Distribution with Retiming Enabled for Synthesis Optimization