Post-Synthesis and Post-Logic Optimization - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

Estimated net delays are close to the best possible placement for all paths. To fix violating paths try the following:

  • Change the RTL.
  • Use different synthesis options.
  • Add timing exceptions such as multicycle paths, if appropriate and safe for the functionality in hardware.