Debugging the NoC - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-05-30
Version
2024.1 English

In Versal devices, the network on chip (NoC) is used for sharing data between IP endpoints in the programmable logic (PL), the CIPS, and other integrated blocks. The NoC components comprise the NoC master unit (NMU), NoC slave unit (NSU), NoC packet switches (NPS), and NoC inter-die bridge (NIDB). For debugging, each NoC component has a set of status registers, which are joined together into interrupt status registers. The interrupts from these registers are routed to the PMC for monitoring, error handling, or subscription by other processing elements. The registers for each component typically include the following:

Performance counters
Determine the bandwidth and latency observed by a component.
Protocol checkers
Check for violations of the AXI specification or component limitations, which is useful when integrating custom PL IP.
Parity and error-correction code (ECC) error checkers
Check for errors in data transmission.
Timeout counters
Check for non-responding components, including one register for upstream and one register for downstream from the component. Timeout counters can also perform some basic latency checks.

Using these registers for debug typically occurs by receiving an interrupt and then querying each NoC component to determine the error source. See the NoC Debug Blog for a tutorial on debugging using these registers. The Versal Adaptive SoC NoC and Integrated Memory Controller NPI Register Reference (AM019) lists NoC registers used for reporting error status and error management.

Every connection through the NoC has an associated QoS requirement. The details of supported QoS settings and their impact for a particular traffic type is discussed in this link in the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313). For guidance on NoC/DDRMC performance tuning, see the Versal Network on Chip/DDR Memory Controller Performance Tuning Tutorial available from the GitHub repository.