CIPS Verification IP - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

The Control, Interfaces, and Processing System (CIPS) Verification Intellectual Property (VIP) supports the functional simulation of Versal adaptive SoC applications. It is targeted to enable the functional verification of programmable logic (PL) by mimicking the processor system (PS)-PL interfaces and OCM memories of PS logic. This VIP is delivered as a package of SystemVerilog modules. VIP operation is controlled by using a sequence of SystemVerilog tasks. For more information, see the Versal Adaptive SoC CIPS Verification IP Data Sheet (DS996).