PS/PMC Peripheral Resets - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

Confirm that the configured peripherals are out of reset.

  • Before initiating requests to any peripheral in the PS or PMC, make sure the peripheral is out of reset.
  • Check all reset registers in CRx (CRL, CRF and CRP) modules.

To read the QSPI reset register using XSCT, run the following command:

xsct%mrd -force 0xF1260300

The expected value from above is 0x0 when QSPI is out of reset.

Table 1. Register RST_QSPI
Register Name Address Width Type Reset Value Description
RST_QSPI 0xF1260300 1 RW 0x00000001 Reset for Individual block
Table 2. Register RST_QSPI Bit-Field Details
Field Name Bits Type Reset Value Description
RESET 0 RW 0x1 Block will be reset when asserted 1