Turn Off Cross-Boundary Optimization - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

Prohibiting cross-boundary optimization in synthesis prevents additional logic getting pulled into a module. This reduces the complexity of the modules but can also lead to higher overall utilization. This can be done globally with the -flatten_hierarchy none option in synth_design. This same technique can be applied on specific modules with the KEEP_HIERARCHY attribute in RTL.