Using SLR Crossing Registers - 2024.1 English

Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388)

Document ID
UG1388
Release Date
2024-06-19
Version
2024.1 English

When targeting SSI technology devices, you can map a register-to-register SLR crossing to a specific CLB TX_REG driving a CLB RX_REG directly through a dedicated SLL route. Using the TX_REG to RX_REG SLR-crossing topology for pipeline register crossings offers the following performance advantages:

  • The placement of SLR crossings spreads vertically, reducing routing congestion near SLR boundaries.
  • Locating registers in SLR crossing slices improves delay estimation accuracy, resulting in higher timing QoR.
  • SLR-crossing performance becomes faster and more consistent.

You can set the USER_SLL_REG property on registers that you expect to be placed at an SLR crossing boundary. The USER_SLL_REG constraint is ignored by place_design if the following is true:

  • The register D and Q pins are connected to a net that does not cross an SLR boundary.
  • The register D and Q pins are connected to a net with fanout > 1.

Following is an example of a USER_SLL_REG constraint:

# USER_SLL_REG
set_property USER_SLL_REG TRUE [get_cells src_slr_i/G1B.SLL_reg[227]]
set_property USER_SLL_REG TRUE [get_cells dest_slr_i/G1B.SLL_reg[227]]

The following figure shows an example of a USER_SLL_REG constraint and the resulting optimal placement and route.

Figure 1. USER_SLL_REG Constraint